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Tenbric

Hardware for electromagnetic survivability.
Analog compute for decisions digital systems cannot make in time, at power, or under attack.
About
A UK semiconductor company developing analog compute for decisions digital systems cannot make in time, at power, or under load.
  • —
    Physical reservoir computing.
    The dynamics of the physical medium do the work that digital processors would otherwise simulate. Same family as optical reservoir computing, with different cost, power and deployment properties.
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    A platform, not a product.
    The same primitives compose across the three defence concepts below, plus industrial condition monitoring and autonomous system accountability. Three concepts; one underlying architecture.
    Defence is the primary focus. Industrial condition monitoring is the near-revenue wedge funding the defence build; robotics and autonomous-system accountability are later platform extensions.
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    Silicon-native. Sub-milliwatt. Edge-ready.
    Built for continuous inference in environments where GPU-class compute is not available, affordable, or operationally acceptable.
Where we are
18 patents filed. Software validated on five industrial domains plus real GPU telemetry. FPGA architecture complete.
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    6/6 bearings detected at 13.9σ above baseline.
    PRONOSTIA · industry benchmark · independently published
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    21/21 fault scenarios. 100/100 state ordering.
    Tennessee Eastman Process · NASA CMAPSS run-to-failure
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    4.68× lower RMSE than best-tuned ESN on real V100 telemetry.
    20.2 hours of live data · 9 tau values swept · Oxford Reveal + ORNL Summit
    Against the best deep-learning baseline (MLP-AE): 4.15× lower RMSE, 39× faster training, 7.4× fewer parameters.
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    0.938 AUC on silent data corruption, where threshold monitoring scores zero.
    Plus +42% earlier warning on VRM failures vs threshold
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    FPGA architecture specification complete.
    First-silicon path · European MPW · 24–36 months
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    18 patents filed covering the underlying primitives.
    Parent filing December 2025 · prosecution active
    Defence-specific embodiments being prepared for additional filing before detailed disclosure.
01
Software validation
6 domains validated
02
IP portfolio
18 patents filed
03
FPGA architecture
Spec complete
04
Commercial engagement
Active now
05
First silicon
24–36 months

Three concepts

One architecture, three surfaces. Control our emissions. Govern automated decisions. Read their interference. Shared primitives, shared IP family, shared path to silicon.
01
APESC-Emit
Transmit without giving away position.
Concept 01
APESC-Emit
Decides, in real time, whether it is safe for a tactical radio to transmit. Suppresses transmissions likely to increase the platform's direction-finding risk.
The threat
Units are abandoning radios because transmitting reveals them.
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    Artillery lands on radio emitters within minutes.
    Russian TORN and Plastun systems, documented across Ukraine, detect a transmission and cue fire before the operator has finished speaking. The threat is deployed, cheap, and proliferating.
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    Procedural EMCON breaks under stress.
    Standard operating procedures ask soldiers to limit transmission exactly when discipline collapses. Doctrine has moved to "don't transmit at all" as the only rule that survives contact.
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    LPI/LPD hides the message, not the fact of transmission.
    Existing waveform work focuses on intercept. APESC-Emit addresses detection — the thing direction-finding actually exploits. Different problem, different layer of the stack.
The counter
Decides, per transmission, whether emitting is survivable.
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    Sits in the transmit-control path.
    PTT/PA-enable gating · accessory-interface control · RF bump-in-the-wire
    Implementation depends on the host radio. No waveform change required; works with existing tactical radios in their current configuration.
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    Permits or blocks transmit at the hardware level.
    A transmission request that would create unacceptable exposure is intercepted before RF energy leaves the antenna. Hardware-enforced, not software-advisory.
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    One policy governs every emitter on the platform.
    Radio + data link + secondary emitters · single policy bus
    The aggregate pattern across emitters is governed from one point of authority, closing the gap a disciplined radio cannot close alone.
The change
Emission discipline stops depending on soldier behaviour.
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    The hardware remembers the rule. The operator doesn't have to.
    Platform-level enforcement holds under fatigue, adrenaline and contact — conditions where procedural EMCON has always failed.
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    Retrofittable to in-service fleets.
    Deployable across existing Falcon III/IV, Tough SDR and SquadNet inventories without waveform change or host-radio redesign — not waiting on the next radio generation.
What exists today
The classification engine runs. The open questions are defence signal, integration, and adversarial testing.
Software
Working reference implementation. Python. Running on real industrial and GPU data.
Validation
6/6 PRONOSTIA bearings at 13.9σ above baseline 21/21 Tennessee Eastman fault scenarios 100/100 NASA CMAPSS state ordering 4.68× lower RMSE vs best-tuned ESN on real V100 telemetry
Open questions
Does the engine carry to RF emission patterns? Which radios, which policy interfaces, which customer hardware? Does it hold up under an adversarial red team?
Build path
Four phases. Each answers one de-risking question.
Path to deployment · indicative
Scope-dependent; subject to refinement under NDA
Phase 01
Software on defence signal
Proves: does the existing engine transfer to RF emission data?
Run the validated software reference on representative RF emission captures. Data partnership + SDR setup. No new hardware.
£80–150k
3–6 months
Phase 02
Radio integration bench
Proves: can it run with a real tactical radio in the loop?
SDR/FPGA bench paired with a specific tactical radio class. Real policy bus, real fail-open behaviour, real commander-override workflow against one customer's doctrine.
£300–500k
6–9 months
Phase 03
Red-team range trial
Proves: does it reduce detectability against a capable ELINT opponent?
Cooperative red team with representative ELINT capability. Hard kill-or-prove event. The thesis survives this trial or it doesn't.
£600k–1M
9–14 months
Phase 04
Analog CMOS ASIC
Proves: do production economics and low-SWaP hold on custom silicon?
Platform-class upgrade for handheld, unmanned and body-worn variants. Only required once the three earlier phases have cleared.
£2–4M
18–24 months
Evidence, unknowns, competitive
What's proven in the building blocks
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    Core analog-compute primitive validated across five industrial domains with independent published datasets (PRONOSTIA bearings, Tennessee Eastman, NASA CMAPSS, CALCE CS2, LBNL boiler).
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    State-machine primitive filed with a working software reference. Suppress / Monitor / Engage logic, refractory hold-off, coincidence detection, policy bus.
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    Operational pain independently citable across US Army FM 3-12 updates, Marine EMCON SOPs, Australian Army doctrine, RUSI and Jamestown on Russian TORN and Plastun artillery-cueing.
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    Specific combination of the two primitives against RF emission has not been demonstrated; the primitives it combines are established.
What's not proven
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    Detectability-state formalism not yet validated against a real ELINT adversary in a range environment. A red-team range test resolves this.
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    Possible that a simpler rule-based policy achieves most of the benefit — in which case architectural distinctiveness narrows to "hardware enforcer of EMCON rules." Still valuable, less differentiated.
Where it sits against the landscape
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    Thales SquadNet "suspend all network transmissions" mode — customer-specific contract. Narrower: software commander-switch inside a single radio family, not a hardware interlock across heterogeneous emitters. Validates the category; doesn't preempt the external-hardware variant. Competitive window on that narrower form: 24–36 months.
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    L3Harris Falcon, Bittium Tough SDR, Rohde & Schwarz, Leonardo S-Wave, Thales Synaps — ESSOR-compliant LPI/LPD waveforms and encryption. No hardware emission-permission interlock we have been able to find in published materials.
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    Academic work (Virginia Tech, Georgia Tech, Stanford) is waveform-level scheduling. Not platform-level hardware.
02
TPRT-Govern
Fail-open governance for automated defence decisions.
Concept 02
TPRT-Govern
Makes automated defence systems safe enough for a commander to deploy. Fails open, survives cyber attack, preserves commander override even under compromise. Payload-agnostic.
The threat
Every automated defence decision fails the commander test.
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    Commanders reject any system that could fail closed.
    Automated emission control, autonomous platform handover, AI-enabled action approval, cyber-isolation of compromised subsystems — all face the same structural objection. No commander authorises automation whose failure mode blocks a mission-critical operation.
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    Firmware compromise is a credible attack path on every class of autonomous defence system.
    An adversary that reaches the firmware running the decision can silence, unlock, or misuse the system without ever touching the payload. Override must live below the main attack surface.
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    The governance question blocks adoption, not the capability question.
    Published capability work has advanced faster than published governance architecture. The deployment bottleneck is not "can we build it" — it is "can a commander sign off on it."
The counter
One governance architecture. Payload-agnostic.
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    Every failure mode defaults safe.
    Fail-open on power-on · fault · watchdog · compromise
    The interlock is additive, never load-bearing. Whatever the governance layer wraps — emission control, autonomous handover, EW response — continues to operate normally if the governance itself fails.
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    Runs on COTS SmartNIC hardware.
    BlueField-3, Alveo, OCTEON, Napatech — hardware you can buy today. SmartNIC-class platforms support sub-microsecond datapath decisions in existing commercial deployments. Working Python reference exists; the port to firmware is engineering, not research.
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    Physical kill-switch under a formally-verified microkernel.
    seL4 · TPM/HSM root of trust · override path outside the main attack surface
    seL4 formally verified on 14+ platforms; defeated a DARPA red team on an Unmanned Little Bird. CBRS SAS is the civilian structural analogue.
The change
Automation becomes something a commander can approve.
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    APESC-Emit is the first application. It is not the only one.
    Emission permission is the near-term integration target because it is the most clearly scoped. The same governance architecture applies to autonomous handover, cognitive EW response, and AI-enabled action approval — every case where hardware-enforced oversight and fail-open safety are deployment prerequisites.
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    The moat is the combination, not any one primitive.
    A prime could build any single primitive. The governance architecture — fail-open bypass, watchdog, three-state degradation, receiver-feedback, cyber-separated override — is a combination that took years to design in the datacentre context and would take years to replicate in defence. No published governed-autonomy layer of this class we have found.
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    Ships as a SmartNIC module. ASIC optional.
    Firmware-on-SmartNIC may remain the permanent product for many deployments. Custom silicon is a platform-class upgrade for the lowest-power use cases, not a mandatory step.
What exists today
The governance architecture runs. The open questions are firmware port, payload integration, and red-team resilience.
Software
Working Python reference. Bypass MUX, watchdog, three-state FSM, receiver-feedback loop. Payload-agnostic by design.
Foundations
seL4 microkernel formally verified on 14+ platforms, defeated a DARPA HACMS red team. SmartNIC hardware achieves sub-microsecond decision latency in existing commercial deployment. CBRS SAS is the civilian structural analogue.
Open questions
Does the architecture hold at real SmartNIC latency? Which first payload, which customer hardware, which operational workflow? Does cyber-separated override survive a capable red team?
Build path
Four phases. Each answers one de-risking question.
Path to deployment · indicative
Scope-dependent; subject to refinement under NDA
Phase 01
Firmware port to COTS
Proves: does the governance layer run at real SmartNIC latency under synthetic failure injection?
Port the existing Python reference to firmware on BlueField-3 or equivalent. Instrumented failure-mode testing across every documented failure path. No new hardware.
£150–250k
4–6 months
Phase 02
First payload integration
Proves: does it handle a real payload in the loop without operator friction?
Integrated with a first payload — APESC-Emit as the most scoped option, or any other customer-specified automated decision system. Real hardware in the loop, real policy authoring, real commander override.
£300–500k
6–9 months
Phase 03
Adversarial cyber-resilience trial
Proves: does commander override survive firmware compromise under attack?
Red-team cyber trial against the governance layer. Structural override path pressure-tested. Hard kill-or-prove event for the cyber-separation claim.
£400–700k
9–14 months
Phase 04
ASIC migration (optional)
Proves: is custom silicon worth it, or is SmartNIC firmware the permanent product?
Platform-class upgrade for lowest-power platforms. Firmware-on-SmartNIC may remain the permanent product for many deployments; ASIC is optional, not mandatory.
£1.5–3M
~18 months
Evidence, unknowns, competitive
What's proven in the building blocks
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    Governance architecture filed with a working Python reference — bypass MUX, watchdog, three-state FSM, receiver-feedback loop.
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    seL4 microkernel formally verified on 14+ platforms including BlueField-adjacent ARMv8/v9 cores. Defeated a DARPA HACMS red team on a Boeing Unmanned Little Bird.
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    SmartNIC hardware achieves sub-microsecond decision latency in existing commercial deployment.
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    CBRS SAS is the structural analogue — external-authorisation spectrum governance validated at civilian scale.
What's not proven
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    Specific combination not yet deployed: governance layer of this class applied to RF transmit control on a SmartNIC with a verified microkernel.
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    Application-layer formal verification of the transmit-control state machine has not been done.
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    Firmware prototype on BlueField-3 resolves both.
Where it sits against the landscape
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    No published governed-emission-permission product on SmartNIC we have been able to find. Industry TRL for the category is low; the opportunity space appears genuinely open.
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    CBRS SAS administrators (Google, CommScope, Federated Wireless, Sony, Amdocs) — civilian spectrum, structural analogue only.
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    seL4 defence deployments (Kry10, Neutrality, DornerWorks) — platform-layer verification, not application-layer governance of this class.
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    DO-254 airborne radio providers (Collins, Rockwell, Honeywell) — safety-qualified but not cyber-emission-governed.
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    SmartNIC defence integrators (NVIDIA + Lockheed / Palantir non-public; Napatech cybersecurity) — no published emission-permission products.
03
HyperNIC
Reads jammers before the receiver even sees them.
Concept 03
HyperNIC
Tells a receiver what kind of jammer is hitting it, before the signal is digitised. Produces a typed interference classification the host uses to choose the right countermeasure.
The threat
Receivers don't know what kind of jammer is hitting them.
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    Disclosed systems filter or cancel. We have not found published systems that produce typed classification.
    DARPA WARP, Northrop APR-39E, BAE ARC appear to focus on interference energy in their public descriptions. Classified or unpublished equivalents may exist; the disclosed space points toward filter/cancel approaches rather than pre-ADC classification.
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    Wrong countermeasure fires against wrong threat.
    Without classification, the host cannot distinguish burst jamming from wideband noise or impulsive interference. Protection engages blindly — which is expensive, and often ineffective.
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    Post-ADC classification is unaffordable on low-SWaP platforms.
    Classifying after the ADC means the ADC must handle the jammer. The bandwidth, power and thermal cost rule the approach out for handheld, unmanned and body-worn systems.
The counter
Classifies the interference before the ADC ever sees it.
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    Taps the RF path. Main receiver unaffected.
    Coupler-based · no insertion loss on primary path
    The classifier is additive, not in-line. No degradation of the signal the main receiver is trying to pull out.
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    Only the classification answer is digitised.
    Two analog stages — coded metasurface for spatial filtering, CMOS temporal tile for time-domain structure — produce a trained readout. The wideband RF never crosses into digital.
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    Typed output, not just a jam flag.
    Burst · narrowband CW · wideband noise · impulsive
    A low-bandwidth decision output the host uses to drive the right protection, AGC, nulling or reconfiguration — with the kind of jammer identified, not just the fact of jamming.
The change
Right protection fires against right threat, at low SWaP.
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    Countermeasures matched to jammer type, not defaulted.
    Burst jamming and wideband noise demand different responses. Classification is what lets the host engage the one that actually works.
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    Sits alongside DARPA WARP, not against it.
    WARP filters and cancels. HyperNIC classifies. Different capability class — layered with, not competing against, US prime EW investment.
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    Viable where digital-domain classification is not.
    Opens the capability to handheld, unmanned and body-worn envelopes that the post-ADC approach rules out on power, bandwidth and thermal budget alone.
What exists today
The approach is modelled. The open questions are physics characterisation, first silicon, and real jammer response.
Literature
Coded metasurfaces at 1–2 bit quantisation widely demonstrated. Memristor reservoir computing published (Nature Electronics 2022). FPGA Boolean reservoir RF modulation classification achieves CNN-competitive accuracy.
Tenbric
Temporal-tile primitive validated in adjacent industrial domains. Physics envelope de-risked relative to earlier framings — switched-coded variant is feasible in standard mixed-signal CMOS.
Open questions
First physical silicon and bench characterisation — the specific regime has not been combined into a demonstrated device in published work. SIR gain against adversarial jammers requires physical bring-up.
Build path
Three phases. Hardware-first, because the device has to exist to be tested.
Path to deployment · indicative
Scope-dependent; subject to refinement under NDA
Phase 01
First-gen silicon prototype
Proves: does the pre-ADC analog classifier work as a physical device?
Switched-coded metasurface, PIN diode switches, mixed-signal CMOS on European MPW, tap coupler, MIL-STD-810 envelope. First bench-characterisable device.
£500–800k
12–18 months
Phase 02
SIR gain characterisation
Proves: does it deliver useful SIR gain against adversarial jammers?
End-to-end characterisation against adversarial jammers. Integrated with host receiver protection. Gate for Gen-2 decision — continue or kill here.
£800k–1.5M
12–16 months
Phase 03
Gen-2 space-rated (optional)
Proves: is the radiation-hardened variant worth the step up?
Ferroelectric continuous-tuning variant for space and high-rad platforms. Only required if the mission envelope demands it.
£3–6M
24–36 months
Evidence, unknowns, competitive
What's proven in the building blocks
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    Temporal-tile primitive validated in adjacent industrial domains.
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    Coded metasurfaces at 1-bit and 2-bit extensively demonstrated in RIS literature for classification and microwave imaging.
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    Memristor reservoir computing for analog signal processing published — Zhong 2022, Nature Electronics.
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    FPGA Boolean reservoir RF modulation classification achieves CNN-competitive accuracy. Quantum reservoir on microwave signals — 2024, Nature Communications.
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    Building blocks exist in the literature. Specific regime has not yet been combined into a demonstrated device.
What's not proven
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    Specific regime — analog, pre-ADC, wideband RF, nanosecond fading memory, CMOS-integrable — has not been experimentally demonstrated in published literature.
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    End-to-end SIR gain above 6 dB on adversarial jammers has not been bench-validated.
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    First-generation physics de-risked relative to earlier framings. Physical bring-up remains to be done.
Where it sits against the landscape
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    DARPA WARP (2020–2025) — multi-prime programme with BAE, Raytheon/Collins, Northrop Grumman, L3Harris, Columbia, Penn, Indiana Microelectronics. Aggregate approximately $30–60M. Filters and cancels (2–18 GHz). Architecturally distinct: WARP filters/cancels; HyperNIC classifies. Complementary if positioned carefully.
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    Northrop APR-39E — in production, TRL 9. Operates on digital RWR architecture per its public description; any pre-ADC analog classification is not disclosed.
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    BAE ARC / CommEx — cognitive EW, TRL 6+ on specific platforms.
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    Roke LOCATE / HMEWC — spectrum monitoring, DF, beamforming. Adjacent function, not the same capability.

How they combine

APESC-Emit is the near-term wedge. TPRT-Govern is the payload-agnostic governance layer — APESC-Emit is its first integration, not its only market. HyperNIC is the longer-horizon receiver-side surface.

The working software reference for APESC-Emit's classifier and TPRT-Govern's architecture means the earliest phases are integration and characterisation, not development. Field-demonstrable artefacts are reachable inside twelve months on cost ranges that a prime's IRAD budget can absorb.

All three share the same production endgame: a mixed-signal CMOS analog-compute chiplet at approximately 3 mm² and under 20 µJ per classification, on the 24–36 month horizon via European MPW. That is the sovereign UK semiconductor capability story under the near-term product paths.

The ask

If you're a prime or integrator
A technical review under NDA with any of the three concepts most relevant to your interests.

Sixty minutes with one or more of your technical people. Focused on the concept you care about most. Architectural and implementation depth available under NDA; the sections above describe each concept at capability level only.

The fastest useful second step, if the first goes well, is a scoped conversation about what engagement would look like — technical collaboration, named sub-prime arrangements, or onward introductions to people in your network we should be speaking to.

Contact
If you're a defence-aligned investor
Funding to complete the first defence validation loop.

First tranche: £80–150k, 3–6 months. Defence-specific IP filing, RF-emission dataset capture, software transfer test of the existing classification engine onto representative RF data, and APESC-Emit integration plan with a named radio class.

That tranche produces a pass/fail signal on the entire defence thesis. If the engine transfers to RF emission data, the next round funds radio integration (£300–500k, 6–9 months) and then red-team range validation (£600k–1M, 9–14 months). If it doesn't, you know early and cheaply.

Contact
Kieran Seebach · Founder, Tenbric · kieran@tenbric.com · Manchester, UK